Since the rise of the data communication industry offering communication facilities specially tailored for the transfer of information in digital form, a class of computers can be identified which is especially adapted for functions related to the communication of data in digital form. For example, the Crager et al U.S. Pat. Nos. 4,058,672 and 4,058,838, both disclose packet switched data communication systems as well as processors specially adapted for performing functions required in such systems. The present invention is an improvement of these and other communication oriented processors.
Taking as an example the above-referenced patents, the functions typically required of the communication processor includes those of:
(1) collecting bit serial information received from one or more communication lines and forming a group of such bits (for example, a byte); PA1 (2) storing the collected bytes and collecting additional bytes; PA1 (3) in the course of collecting the first or subsequent bytes, performing any necessary code translation or parity or other type of data checking; PA1 (4) when a group of bytes are collected (for example, a packet) processing them and then outputting the packet through another port for transmission to another communication processor or to the data recipient.
While the performance of these functions is, in and of itself, conventional in the art, the function of the communication processor is to perform the foregoing function simultaneously for a large number of communication lines over which data may be received, to do so efficiently as the information transfer rate varies as a function of time, and do so in a manner in which the capacity of the communication processor can be changed (usually increased) due to the addition of new communication lines and perform the foregoing functions in a reliable and maintainable system, which has the further characteristic of being reasonable in cost. Although the example given above has been that of a node or a switch in a packet data transmission system, those skilled in the art will understand that the same apparatus should also be capable of concentration, multiplexing and message switching.
It is, of course, a trivial solution to the problem of efficient growth in a node in a data switching system, to provide a processor having capacity equal to the largest capacity then foreseen for the particular node. Not only is the solution trivial but is also impractical, especially where when initially installed the node does not require the amount of processing power ultimately foreseen.
A particularly effective solution for this problem is to provide for processing power in increments, but a pressing problem raised by this solution is that of integrating each new increment of processing power into the extant system in a manner which does not detract from the efficiency of the already-available processing power. This is a problem inherent in any distributed computing system and the solution of the problem disclosed herein is applicable not only to communication processors but to any distributed computer.
The patents to Deerfield (U.S. Pat. No. 3,932,841) and Nutter (U.S. Pat. No. 4,059,851) provide an arrangement in which information may be transferred over a common bus coupling major components of a digital computer system. In both systems, a priority scheme is implemented by passing a control signal along a serial path from a source of the signal to the highest priority user and from that user to a lower priority user, and so on. The signal, received at a user, is only passed on after the user accesses the bus. While these arrangements should be quite effective, they do admit of substantial improvement. In a system which may be limited by bus capacity, saving the time which would be otherwise wasted between the completion of one access by a user to allow the control signal to trickle down to another user, can make an enormous difference.
Furthermore, Deerfield explicitly, and Nutter implicitly teach that a bus user can use the bus for an unlimited time without relinquishing access. While this may be workable in a generalized digital computer environment, in the environment of a communication processor, it is not a viable technique.
It is therefore one object of the present invention to provide a flexible modular distributed computer which is capable of allocating a common resource among a variable number of processor users of that resource. It is a more particular object of the present invention to provide a distributed computing system in which access to a common memory resource is distributed over a demand assigned bus which provides for equal availability of the bus to a variable number of processor users. A further object of the invention is to provide for the distribution of the demand assigned bus in a fashion which does not waste bus resource capacity in making the decision as to which processor user will next have access to the bus. It is a further object of the present invention to provide for a distributed computing system in which a plurality of processor users access a common memory over a demand assigned bus and in which bus resource is not wasted in waiting for the common memory to complete an information transfer cycle. It is another object to provide a demand assigned bus distribution system in which a user gaining access is only permitted to use the bus for a single transfer, must thereafter relinquish the bus and can only regain the bus after each other user has accessed the bus or refused access.
It is still another object of the invention to provide a communication processor having a plurality of line processors and at least one executive or background processor, in which each of the line processors communicates with a common memory over a demand assigned bus in an effective and efficient manner. It is another object of the invention to provide for a variable number of line processors, and the capability of adding additional line processors without interrupting the operation of the processor.
It is still another object of the invention to provide a communication processor including a variable number of line processors and common equipment including a memory, demand assigned bus, an executive or background processor in which the common equipment can be configured in fully redundant form. It is another object of the invention to provide a system of the foregoing type in which the executive or background processor can override each of the line processors and require them to operate on one of the two buses.
It is yet another object of the invention to provide a communication processor including a plurality of line processors, one for each communication or groups of communication lines in which the line processors are coupled to the communication lines over interface switches and in which an executive or background processor has the capability of removing any identified line processors.